1. Field of the Invention
The present invention relates in general to digital video cassette recorders, and more particularly to a video data recording apparatus for a digital video cassette recorder for recording input video data in a shuffling manner to obtain a distinct picture quality.
2. Description of the Prior Art
Generally, in a digital recording format of a digital video cassette recorder (referred to hereinafter as VCR), an input video signal is pulse code-modulated (PCM) and pixel values thereof are then coded in the unit of a desired bit. Namely, the input video signal is converted into digital video data, which is then compressed by a variable length coding which varies a length of bit being coded every pixel. The digital video data compressed by the variable length coding is partitioned in the unit of a desired sync-block and then recorded on a video tape in a predetermined order.
In a change-speed playback mode which is one of special functions of the digital VCR, the video data recorded on the video tape is scanned by a head disposed in a spiral form, being divided into playback portions A and covered-up portions or no-playback portions B as shown in FIG. 1, which is a view illustrating a trace of the head for the playback of the video data recorded on the video tape. As a result, only the playback portions A are repeatedly scanned.
For the purpose of preventing a degradation in a picture quality due to the no-playback portions B, the playback portions A and the no-playback portions B are shuffled with each other and then recorded on the video tape. As a result, the shuffled video data are recorded and played back. The shuffling of the video data is an important factor of determining the recording format.
Referring to FIG. 2, there is shown a block diagram of a conventional video data recording apparatus for the digital VCR. As shown in this drawing, the conventional video data recording apparatus comprises a control signal generation circuit 1 for generating a vertical synchronous signal Vsyn, a write clock signal and a switching signal S1 in response to input video data V1 of one frame a delay unit 2 for delaying the input video data Vi by a predetermined time period, a buffer 3 for shuffling the input video data V1 and the delayed video data Vi' from the delay unit 2, and a recording circuit 4 for amplifying output video data V1 from the buffer 3 by a predetermined level, adding a synchronous signal SYN and an identification signal Id to the amplified video data and recording the resultant video data on the video tape.
A switch SW2 is adapted to selectively transfer one of the input video data Vi and the delayed video data Vi' from the delay unit 2 to the buffer 3.
A switch SW1 is adapted to selectively transfer the input video data Vi to the delay unit 2 and the switch SW2 in response to the switching signal from the control signal generation circuit 1.
The operation of the conventional video data recording apparatus with the above-mentioned construction will hereinafter be described with reference to FIGS. 2 and 3.
FIG. 3 is a view illustrating the shuffled video data in FIG. 2. A unit of a shuffling size of the video data on the video tape is a segment, which is the minimum codable unit with a predetermined size. The segments are shifted along tracks of the video tape. As shown in FIG. 3, the video data recorded on the video tape is shuffled so that the sync-blocks can repeatedly be detected from the video data.
In operation, upon receiving the input video data Vi the control signal generation circuit 1 generates the vertical synchronous signal Vsyn for the synchronization of the input video data Vi and the write clock signal for the recording of the input video data Vi. Also, the control signal generation circuit 1 generates the switching signal S1 for the control of the switches SW1 and SW2, In response to the switching signal S1 from the control signal generation circuit 1, the switches SW1 and SW2 perform the switching operations so that the input video data Vi can be transferred to the buffer 3.
Upon application of the input video data Vi of one-frame to the buffer 3 through the switches SW1 and SW2, the switches SW1 and SW2 perform the switching operations in response to the switching signal S1 from the control signal generation circuit 1 so that the input video data Vi can be transferred to the delay unit 2 and the delayed video data Vi' from the delay unit 2 can be transferred to the buffer 3.
The input video data Vi and the delayed video data Vi' from the delay unit 2 are shuffled by the buffer 3 as shown in FIG. 3.
Namely, the video data of one frame tape is divided in the unit of segment. The video-data of the divided segments are shuffled as shown in FIG. 3. For example, in the case where the video data is divided into four segments in each track and it is played back in a four times speed playback mode, the video data of the first segment (1,1) of the first track is repeatedly recorded on a position of the fourth segment (5,4) of the fifth track. Also, the video data of the second segment (1,2) of the first track is recorded on a position of the first segment (5,1) of the fifth track. In this manner, the shuffling is performed.
At this time, the optimum multi-speed is determined according to the size of the segment shuffled by the buffer 3 to obtain a distinct picture quality.
With the shuffling completed, the output video data from the buffer 3 is amplified by the predetermined level by the recording circuit 4. Then, the recording circuit 4 adds the synchronous signal SYN and the identification signal Id to the amplified video data and records the resultant video data on the video tape.
However, the above-mentioned conventional video data recording apparatus has a disadvantage in that the time and effect of the no-playback portions are different according to the multi-speeds tracing the tracks. Namely, the optimum multi-speed is determined according to the size of the shuffled segment and the time and effect of the no-playback portions in other multi-speeds are in proportion to a distance of the optimum multi-speed. This results in a degradation in the picture quality.